Universal Asynchronous Receiver and Transmitter (UART)

 Display “Hello World” message using Internal UART.

THEORY:

The LPC1768 contain four UART's. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode.

The UART's include a fractional baud rate generator. Standard baud rates such as 115200 Baud can be achieved with any crystal frequency above 2 MHz.

UART module and registers:

• LPC1768 has 4-UARTs numbering 0-3, similarly the pins are also named as RXD0-RXD3 and TXD0-TXD3.
• As the LPC1768 pins are multiplexed for multiple functionalities, first they have to be configured as UART pins.
• Below table shows the multiplexed UARTs pins.

Port Pin	Pin Number	PINSEL_FUNC_0	PINSEL_FUNC_1	PINSEL_FUNC_2	PINSEL_FUNC_3
P0.02	98	GPIO	TXD0	ADC0[7]
P0.03	99	GPIO	RXD0	ADC0[6]
P2_0	48	GPIO	PWM1[1]	TXD1
P2.1	49	GPIO	PWM1[2]	RXD1
P0.10	62	GPIO	TXD2	SDA2	MAT3[0]
P0.11	63	GPIO	RXD2	SCL2	MAT3[1]
P0.0	82	GPIO	CAN1_Rx	TXD3	SDA1
P0.1	85	GPIO	CAN1_Tx	RXD3	SCL1

UART Registers:

Register	Description
RBR	Receiver Buffer Register. Contains the recently received Data
THR	Transmit Holding Register. The next character to be transmitted is written here.Contains the data to be transmitted
FCR	FIFO Control Register FIFO Control Register
LCR	Line Control Register Controls the UART frame formatting(Number of Data Bits, Stop bits)
DLL	Divisor Latch LSB. Least Significant Byte of the UART baud rate generator value.
DLM	Divisor Latch MSB Most Significant Byte of the UART baud rate generator value.
IER .	Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts

UART Register Configuration:

FCR ( FIFO Control Register )

LPC1768 has inbuilt 16byte FIFO for Receiver/Transmitter. Thus it can store 16-bytes of data received on UART without overwriting. If the data is not read before the Queue(FIFO) is filled then the new data will be lost and the OVERRUN error bit will be set.

FCR
31:8	7:6	5:4	3	2	1	0
RESERVED	RX TRIGGER	RESERVED	DMA MODE	TX FIFO RESET	RX FIFO RESET	FIFO ENABLE

Bit 0 – FIFO:
This bit is used to enable/disable the FIFO for the data received/transmitted.
0--FIFO is Disabled.
1--FIFO is Enabled for both Rx and Tx.

Bit 1 – RX_FIFO:
This is used to clear the 16-byte Rx FIFO.
0--No impact.
1--CLears the 16-byte Rx FIFO and the resets the FIFO pointer.

Bit 2 – Tx_FIFO:
This is used to clear the 16-byte Tx FIFO.
0--No impact.
1--Clears the 16-byte Tx FIFO and the resets the FIFO pointer.

Bit 3 – DMA_MODE:
This is used for Enabling/Disabling DMA mode.
0--Disables the DMA.
1--Enables DMA only when the FIFO(bit-0) bit is SET.

Bit 7:6 – Rx_TRIGGER:
This bit is used to select the number of bytes of the receiver data to be written so as to enable the interrupt/DMA.
00-- Trigger level 0 (1 character or 0x01)
01-- Trigger level 1 (4 characters or 0x04)
10-- Trigger level 2 (8 characters or 0x08)
11-- Trigger level 3 (14 characters or 0x0E) 

LCR ( Line Control Register )

This register is used for defining the UART frame format ie. Number of Data bits, STOP bits etc.

LCR
31:8	7	6	5:4	3	2	1:0
Reserved	DLAB	Break COntrol	Parity Select	Parity Enable	Stop Bit Select	Word Length Select

Bit 1:0 – WLS : WordLenghtSelect
These two bits are used to select the character length
00-- 5-bit character length
01-- 6-bit character length
10-- 7-bit character length
11-- 8-bit character length

Bit 2 – Stop Bit Selection:
This bit is used to select the number(1/2) of stop bits
0-- 1 Stop bit
1-- 2 Stop Bits

Bit 3 – Parity Enable:
This bit is used to Enable or Disable the Parity generation and checking.
0-- Disable parity generation and checking.
1-- Enable parity generation and checking.

Bit 5:4 – Parity Selection:
These two bits will be used to select the type of parity.
00-- Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
01-- Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
10-- Forced "1" stick parity.
11-- Forced "0" stick parity 

Bit 6 – Break Control
0-- Disable break transmission.
1-- Enable break transmission. Output pin UARTn TXD is forced to logic 0

Bit 8 – DLAB: Divisor Latch Access Bit
This bit is used to enable the access to divisor latch.
0-- Disable access to divisor latch
0-- Enable access to divisor latch 

LSR (Line Status Register)

This is a read-only register that provides status information of the UART TX and RX blocks.

LSR
31:8	7	6	5	4	3	2	1	0
Reserved	RXFE	TEMT	THRE	BI	FE	PE	OE	RDR

Bit 0 – RDR: Receive Data Ready
This bit will be set when there is a received data in RBR register. This bit will be automatically cleared when RBR is empty.
0-- The UARTn receiver FIFO is empty.
1-- The UARTn receiver FIFO is not empty.

Bit 1 – OE: Overrun Error
The overrun error condition is set when the UART Rx FIFO is full and a new character is received. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.
0-- No overrun
1-- Buffer over run

Bit 2 – PE: Parity Error
This bit is set when the receiver detects a error in the Parity.
0-- No Parity Error
1-- Parity Error

Bit 3 – FE: Framing Error
This bit is set when there is error in the STOP bit(LOGIC 0)
0-- No Framing Error
1-- Framing Error

Bit 4 – BI: Break Interrupt
This bit is set when the RXDn is held in the spacing state (all zeroes) for one full character transmission
0-- No Break interrupt
1-- Break Interrupt detected.

Bit 5 – THRE: Transmitter Holding Register Empty
THRE is set immediately upon detection of an empty THR. It is automatically cleared when the THR is written.
0-- THR register is Empty
1-- THR has valid data to be transmitted

Bit 6 – TEMT: Transmitter Empty
TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when any of them contain valid data.
0-- THR and/or the TSR contains valid data.
1-- THR and the TSR are empty.

Bit 7 – RXFE: Error in Rx FIFO
This bit is set when the received data is affected by Framing Error/Parity Error/Break Error.
0-- RBR contains no UARTn RX errors.
1-- RBR contains at least one RX error.

TER (Transmitter Enable register)

This register is used to Enable/Disable the transmission

TER
31:8	7	6-0
Reserved	TXEN	Reserved

Bit 7 – TXEN: Trsnamitter Enable

When this bit is 1, the data written to the THR is output on the TXD pin.

If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again.

In other words, a 0 in this bit blocks the transfer of characters.

Note: By default this bit will be set after Reset.

Baudrate Calculation

LPC1768 generates the baud rate depending on the values of DLM,DLL.
Baudrate = PCLK/ (16 * ( 256 * DLM + DLL) * (1+ DivAddVal/MulVal))

   

UART_PCLK	PCLK
0	SystemFreq/4
1	SystemFreq
2	SystemFreq/2
3	SystemFreq/8

Getting the PCLK value.

PCLKSELx registers contains the PCLK info for all the clock dependent peripherals in which Bit6,Bit7 contains the Uart Clock(ie.UART_PCLK) information.
The UART_PCLK and the actual Peripheral Clock(PCLK) is calculated as below.
(Refer data sheet for more info)

DivAddVal/MulVal == 0

Using the above parameters , DLL/DLM is calculated as below.
(256 * DLL + DLM) = PCLK / (16* Baudrate).

Steps for Configuring UART0

Below are the steps for configuring the UART0.

1.     Step1: Configure the GPIO pin for UART0 function using PINSEL register.

2.     Step2: Configure the FCR for enabling the FIXO and Reste both the Rx/Tx FIFO.

3.     Step3: Configure LCR for 8-data bits, 1 Stop bit, Disable Parity and Enable DLAB.

4.     Step4: Get the PCLK from PCLKSELx register 7-6 bits.

5.     Step5: Calculate the DLM,DLL vaues for required baudrate from PCLK.

6.     Step6: Updtae the DLM,DLL with the calculated values.

7.     Step6: Finally clear DLAB to disable the access to DLM,DLL.

After this the UART will be ready to Transmit/Receive Data at the specified baudrate.

Program:

  

#include<LPC17xx.h>

void delay(unsigned int r1);

void UART0_Init(void);

void UART0_IRQHandler(void);

unsigned long int r=0, i = 0;

unsigned char tx0_flag=0;

unsigned char *ptr, arr[] = "Hello world\r";

int main(void)

{

            SystemInit();

            SystemCoreClockUpdate();

            UART0_Init();

            while(1)

            {

                        ptr = arr;

                        while ( *ptr != '\0'){

                                    LPC_UART0->THR = *ptr++;

                                    while(tx0_flag == 0x00);

                                    tx0_flag = 0x00;

                        }

                        for (i=0; i<500; i++)

                        delay(625);                              //delay

            }

}

void UART0_Init(void)

{

            LPC_SC->PCONP |= 0x00000008;                           //UART0 peripheral enable

            LPC_PINCON->PINSEL0 &= ~0x000000F0;

            LPC_PINCON->PINSEL0 |= 0x00000050;

            LPC_UART0->LCR = 0x00000083;                       //enable divisor latch, parity disable, 1 stop bit, 8bit word length

            LPC_UART0->DLM = 0X00;

            LPC_UART0->DLL = 0x13;                                     //select baud rate 9600 bps

            LPC_UART0->LCR = 0X00000003;

            LPC_UART0->FCR = 0x07;

            LPC_UART0->IER = 0X03;                                           //select Transmit and receive interrupt

            NVIC_EnableIRQ(UART0_IRQn);                                //Assigning channel

}

void UART0_IRQHandler(void)

{

            unsigned long Int_Stat;

            Int_Stat = LPC_UART0->IIR;               //reading the data from interrupt identification register

            Int_Stat = Int_Stat & 0x06;                        //masking other than txmit int & rcve data indicator

            if((Int_Stat & 0x02)== 0x02)                         //transmit interrupt

                        tx0_flag = 0xff;

}

void delay(unsigned int r1)

{

            for(r=0;r<r1;r++);

} 

--------------------------------------------------------------------------------------------------------------------------

TEST UART0 test:

Download the file “UART0_test.hex” to trainer using Flash Magic 6.01 version.

Switch off SW3, Un-short JP7.

Press the reset switch (SW1) to run the program.

Result:

Open the hyper terminal, the Constant string “Hello World” will be displayed on the hyper terminal.